The present invention relates to a semiconductor memory device, and specifically to a positional relationship between core circuits, such as row decoders or column decoders for selecting memory cells, and control circuits corresponding to the core circuits.
Semiconductor memory devices are constituted mainly by memory cells, which are minimum units for storing data, respectively. Each of the memory cells is an element for storing either a high or low level value. The memory cells are arranged in a matrix format to form the memory cell array of a semiconductor device, such as a DRAM or a clock-synchronism DRAM. The memory cells are selected by word lines in the row directions, and by column-selection lines in the column directions. The word lines and the column-selection lines are connected to a row-selection mechanism and a column-selection mechanism for selecting the lines on the basis of address signals. One of the memory cells in the memory cell array is selected by means of cooperation of the row- and column-selection mechanisms.
FIG. 7 is a view schematically showing the plan layout of a row-selection mechanism or a column-selection mechanism in a semiconductor memory device according to a related art of the present invention.
As shown in FIG. 7, the row- or column-selection mechanism includes an array 11 (or circuit group stage CA) of core circuits, such as row decoders or column decoders, and an array 12 (or circuit group stage CB) of control circuits corresponding to the core circuits.
The core circuit array 11 constituting the circuit group stage CA has an m-number of core circuit units 11g which are substantially the same as or equivalent to each other. Each of the core circuit units 11g consists of an n-number of core circuits 11r which form decoders, respectively. The n-number of core circuits 11r are disposed side by side in a first direction D1, which is parallel to the row or column directions, to constitute each of the core circuit units 11g. The m-number of core circuit units 11g are disposed side by side in the first direction D1 with a pitch Px to constitute the core circuit array 11.
On the other hand, the control circuit array 12 constituting the circuit group stage CB, which is arranged adjacent to the circuit group stage CA, has an m-number of control circuit units 12g which are substantially the same as or equivalent to each other. The control circuit units 12g are connected to the core circuit units 11g by interconnection wiring lines, respectively. The m-number of control circuit units 12g are disposed side by side in the first direction D1 with a pitch Py to constitute the control circuit array 12.
As shown in FIG. 7, the pitches Px and Py of the core circuit units 11g and the control circuit units 12g are set to be the same as each other. In other words, each pair of corresponding core and control circuit units 11g and 12g are arranged to have the same width and be aligned in position with each other in the array direction or first direction D1. Non-corresponding circuits, the number of which does not have to be the same as the m-number of the core circuit units 11g, are arranged outside the circuit group stages CA and CB. Those ones of the lead-out wiring lines from the core circuit array 11, which cannot pass through in the control circuit units 12g, are led out laterally from the circuit group stages CA and CB in the first direction D1.
In the structure shown in FIG. 7, the positional relationship between the core circuit units 11g and the control circuit units 12g, and the positional relationship between the units 11g and 12g and the lead-out wiring lines are restricted, thereby lowering flexibility in design. Further, how to arranged the non-corresponding circuits along with other peripheral circuits outside the circuit group stages CA and CB must be considered, thereby causing the design to be complicated, and causing the occupation surface area of the device or chip to be large.